This invention relates to a nonvolatile semiconductor memory device using nonvolatile memory cells.
Electrically erasable and programmable read only memories (EEPROM) or erasable and programmable read only memory (EPROM) using nonvolatile memory cells have long been known. Each of the memory cells has a double layered gate structure comprising a floating gate and a control gate. Data can be electrically written into and erased from the memory cells.
Each nonvolatile memory cell can be structurally illustrated in the form of an MOS (metal oxide semiconductor) transistor, as shown in FIGS. 1A to 1D. In FIGS. 1A through 1D, 101 and 102 are source and drain regions, respectively. A floating gate electrode, denoted by 103, which is in an electrically floating state, is made of, for example, polycrystalline silicon. A control gate electrode, denoted by 104, is similarly made of, for example, polycrystalline silicon. A relatively thick insulating film of, for example, a silicon oxide film, exists between floating gate electrode 103 and semiconductor substrate 105, and between floating gate electrode 103 and control gate 104. Relatively thin insulating film 107 of, for example, a silicon oxide film, is formed on substrate 105, where floating gate electrode 103 closes drain region 102.
Data is set into the memory cell by injecting electrons into floating gate 103 of the cell. When electrons are injected into floating gate 103, the threshold value of the cell transistor is high. Consequently, even if a high voltage is applied to control gate 104, the transistor is not turned on. When electrons have been discharged from the memory cell, the cell transistor is turned on, providing a high voltage is applied to control gate 104. By detecting the on or off state of the cell transistor, "1" or "0" data of the cell is determined. To inject electrons into floating gate 103, a high voltage is applied to control gate 104. As a result of the application of this high potential, the potential at floating gate 103 is increased through the capacitor coupling between control gate 104 and floating gate 103. Then, electrons are injected from drain 102 into floating gate 103 through thin region 107 of insulating film 106. To discharge electrons from floating gate 103, control gate 104 is grounded, while drain region 102 is set to a high potential. In turn, electrons are discharged from floating gate 103 to drain region 102 through thin region 107 of insulating film 106.
The memory device comprises memory cells arranged in a matrix fashion. To write data into the selected cell, a high voltage must be selectively applied to the control gate electrode. To obtain the high voltage, some of the memory devices contain boost circuits. In this type of memory device, a power source voltage of 5V, for example, can be boosted to, for example, 20V. An example of such a boost circuit is shown in FIG. 2. Timing charts of pulse signals .phi.1 and .phi.2, used to control the operation of the boost circuit, are shown in FIGS. 3A and 3B.
The known boost circuit comprises a plurality of enhancement type MOS transistors 201 serving as diodes, and a plurality of capacitors 202. Under control of pulse signals .phi.1 and .phi.2, the boost circuit can boost a 5V power source voltage Vc to as high a voltage V.sub.H as 20V, for example. This 20V high voltage V.sub.H, however, provides only a weak current. To selectively apply this voltage to the memory cells, no current must be fed from the boost circuit to the nonselected memory cells: those memory cells whose control gate electrodes are grounded. Instead, the boosted voltage must be applied to the selected memory cells. Such a data write circuit needs an increased number of circuit elements; hence its construction is complicated. Similarly, as the conventional memory device is provided with a data write circuit for each row or column line, the memory device contains a large number of elements. Consequently, when fabricating an integrated circuit, the resultant chip is large in size.
A circuit diagram of a conventional EPROM is shown in FIG. 4. Memory cells TM11 to TMmn, as MOS transistors of the double layered gate (floating and control gates) structure, are located at the cross points of row lines R1 to Rm and column lines D1 to Dn. The sources of memory cells TM11 to TMmn are all grounded. Memory cells TM11 to TMmn cooperate to form memory cell array 10.
Row lines R1 to Rm are connected to row decoder 20 through depletion type (D type) MOS transistors TR1 to TRm. Control signal R/W is applied to the gates of transistors TR1 to TRm to control data read/write. Row decoder 20 receives a row address signal (not shown) and selects one of the row lines accordingly, and sets the selected line to a high potential.
Column lines D1 to Dn are connected to signal detection node N1, through enhancement type (E type) MOS transistors TD1 to TDn. Sense amplifier 40 is connected to node N1. Output circuit 50 is connected to amplifier 40. A signal at node N1 is detected by amplifier 40 and output to the exterior through output circuit 50.
Column select lines C1 to Cn are connected to the gates of transistors TD1 to TDn, respectively. Lines C1 to Cn are connected to column decoder 60 through D type MOS transistors TC1 to TCn. Control signal R/W is applied to the gates of transistors TC1 to TCn. Decoder 60 selects one of column select lines C (generally designated as C1 to Cn) according to a column address signal, and sets it to a high potential.
Write circuit 70 selectively feeds high voltage V.sub.H to row line R (generally designates R1 to Rm) and column select line C. Voltage V.sub.H is for writing data, and is obtained by the voltage boost circuit of FIG. 2. Boosted voltage distributing circuits 71.sub.1 to 72m, of a total of (n+m), are provided to correspond to column select lines C1 to Cn and row lines R1 to Rm. Circuits 71 and 72 (generally designated as 71.sub.1 to 71n and 72.sub.1 to 72m) are each comprised of four D type MOS transistors TW1 to TW4, and one E type MOS transistor TW5, as typified by circuit 72.sub.1 which is connected to row line R1. The first ends of transistors TW1 and TW2 are connected to power source terminal 73, coupled with voltage V.sub.H, and power source terminal 74, coupled with power source voltage Vc of, for example, 5V, respectively. The second ends of these transistors are connected together at node 75. Transistor TW3 is connected between node 75 and row line R1. The gates of both transistors TW1 and TW3 are connected together to row line R1. Transistors TW4 and TW5 are inserted in series between terminal 76, connected to voltage Vc, and the ground potential point. Connection point 77, between these transistors, is connected to the gates of transistors TW2 and TW4. The gate of transistor TW5 is connected to row line R1.
E type MOS transistor T1 is connected between node N1 and terminal 78 which is connected to voltage V.sub.H. The gate of transistor T1 is supplied with a signal appearing at output node N2 of write data input control circuit 80.
Circuit 80 is comprised of power source terminal 82, NAND gate circuit 83, and voltage output control circuit 84. NAND gate 83 includes D type MOS transistor T2 and E type MOS transistors T3 and T4, which are connected in series between ground and power source terminal 82 which is connected to voltage Vc. Voltage output control circuit 84 includes D type transistors TW11 to TW13, and E type transistor TW14, and controls voltage V.sub.H according to a signal appearing at output node N3 of NAND gate circuit 83. In NAND gate circuit 83, the gate of transistor T2 is connected to its output node N3. The gate of transistor T3 is supplied with input data Din. The gate of transistor T4 is supplied with signal R/W which is set at level "1" in a write mode and at "0" in a read mode.
In the read mode of the EPROM thus arranged, signal R/W is set at high ("1" ) level, signal R/W at low ("0" ) level, and voltage V.sub.H at power source terminal 73 at 5V. When signal R/W is high in level, transistors TC1 to TCn, and transistors TR1 to TRm are turned on. When signal R/W is low, transistor T4 is turned off, the signal at output node N3 of NAND circuit 83 is set to high level, the signal at output node N2 of output control circuit 84 is set to low level, and transistor T1 is turned off.
Of row lines R1 to Rm and column select lines C1 to Cn, only those selected by row decoder 20 or column decoder 60 are set at high level. Then, memory cell Tm (generally designated as TM11 to TMmn) in memory cell array 10, located at this intersecting point, is selected. If no carriers are injected into selected memory cell TM, the memory cell is turned on, allowing current to flow between the drain and source. If carriers are injected into selected memory cell TM, the memory cell is turned off and signal detecting node N1 is set to high level by the load in sense amplifier 40. The signal at node N1 at this time is output to the exterior through sense amplifier 40 and output circuit 50.
When "1" level data is written into the cell, signal R/W is set to low level, signal R/W to high level, and voltage V.sub.H l to positive 20V. At this time, if row line R1 and column select line C1, for example, are selected, the "1" level voltage is applied to row line R1 and column select line C1, through transistors TR1 and TC1. Then, boosted voltage distribution circuits 71.sub.1 and 72.sub.2, connected to row line R1 and column select line C1, produce high voltage V.sub.H. Row line R1 and column select line C1 are charged up to 20V. As for other row line R and column select line C, the output signals which are derived from row decoder 20 and column decoder 60 are low in level, and boosted voltage distributing circuits 71 and 72 do not produce high voltage H.sub.H. At this time, input data Din is set to high level. As a result, voltage Vc, having been supplied to power source terminal 82, appears at node N3. Therefore, output node N2 of voltage output control circuit 84 is set at V.sub.H, so that transistor T1 is turned on. In turn, transistor TD1, controlled by column select line C1, is turned on to charge column line D1 with a high voltage. The high voltage is applied to the control gates of memory cell TM11, selected by row and column lines R1 and D1, and subsequently, to its drain, with the result that data of "1" level is written into memory cell TM11 by the injection of electrons caused by the tunnel effect. If input data Din is set to low level, the transistor T1 is turned off, so that high voltage is not applied to the drain of memory cell TM11. Accordingly, data of "1" level is not written into the cell (This operation is equivalent to the writing of "0" level into the cell).
When "1" level data has been written into a memory cell, it is retained unless erased. In this respect, the cell data is nonvolatile. The conventional non-volatile semiconductor memory device, however, needs boosted voltage distribution circuits for each row line and each column select line. This results in an increase in the number of circuit elements required for the memory device as a whole, resulting in reduction of packing density when the device is fabricated by IC technology.